212 lines
8.7 KiB
C++
212 lines
8.7 KiB
C++
/*
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Copyright (c) 2013-2023, Intel Corporation
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SPDX-License-Identifier: BSD-3-Clause
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*/
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///////////////////////////////////////////////////////////////////////////////
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// //
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// This file is a standalone program, which detects the best supported ISA. //
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// //
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///////////////////////////////////////////////////////////////////////////////
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#include <stdio.h>
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#if defined(_WIN32) || defined(_WIN64)
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#define HOST_IS_WINDOWS
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#include <intrin.h>
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#elif defined(__APPLE__)
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#define HOST_IS_APPLE
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#endif
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#if !defined(__arm__) && !defined(__aarch64__) && !defined(_M_ARM64)
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#if !defined(HOST_IS_WINDOWS)
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static void __cpuid(int info[4], int infoType) {
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__asm__ __volatile__("cpuid" : "=a"(info[0]), "=b"(info[1]), "=c"(info[2]), "=d"(info[3]) : "0"(infoType));
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}
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static void __cpuidex(int info[4], int level, int count) {
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__asm__ __volatile__("cpuid" : "=a"(info[0]), "=b"(info[1]), "=c"(info[2]), "=d"(info[3]) : "0"(level), "2"(count));
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}
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#endif // !HOST_IS_WINDOWS
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static bool __os_has_avx_support() {
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#if defined(HOST_IS_WINDOWS)
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// Check if the OS will save the YMM registers
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unsigned long long xcrFeatureMask = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
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return (xcrFeatureMask & 6) == 6;
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#else // !defined(HOST_IS_WINDOWS)
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// Check xgetbv; this uses a .byte sequence instead of the instruction
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// directly because older assemblers do not include support for xgetbv and
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// there is no easy way to conditionally compile based on the assembler used.
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int rEAX, rEDX;
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__asm__ __volatile__(".byte 0x0f, 0x01, 0xd0" : "=a"(rEAX), "=d"(rEDX) : "c"(0));
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return (rEAX & 6) == 6;
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#endif // !defined(HOST_IS_WINDOWS)
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}
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static bool __os_has_avx512_support() {
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#if defined(HOST_IS_WINDOWS)
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// Check if the OS saves the XMM, YMM and ZMM registers, i.e. it supports AVX2 and AVX512.
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// See section 2.1 of software.intel.com/sites/default/files/managed/0d/53/319433-022.pdf
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unsigned long long xcrFeatureMask = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
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return (xcrFeatureMask & 0xE6) == 0xE6;
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#elif defined(HOST_IS_APPLE)
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// macOS has different way of dealing with AVX512 than Windows and Linux:
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// - by default AVX512 is off in the newly created thread, which means CPUID flags will
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// indicate AVX512 availability, but OS support check (XCR0) will not succeed.
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// - AVX512 can be enabled either by calling thread_set_state() or by executing any
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// AVX512 instruction, which would cause #UD exception handled by the OS.
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// The purpose of this check is to identify if AVX512 is potentially available, so we
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// need to bypass OS check and look at CPUID flags only.
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// See ispc issue #1854 for more details.
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return true;
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#else // !defined(HOST_IS_WINDOWS)
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// Check xgetbv; this uses a .byte sequence instead of the instruction
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// directly because older assemblers do not include support for xgetbv and
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// there is no easy way to conditionally compile based on the assembler used.
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int rEAX, rEDX;
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__asm__ __volatile__(".byte 0x0f, 0x01, 0xd0" : "=a"(rEAX), "=d"(rEDX) : "c"(0));
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return (rEAX & 0xE6) == 0xE6;
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#endif // !defined(HOST_IS_WINDOWS)
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}
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static bool __os_enabled_amx_support() {
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#if defined(HOST_IS_WINDOWS)
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// Check if the OS will save the YMM registers
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unsigned long long xcrFeatureMask = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
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return (xcrFeatureMask & 0x60000) == 0x60000;
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#else // !defined(HOST_IS_WINDOWS)
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// Check xgetbv; this uses a .byte sequence instead of the instruction
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// directly because older assemblers do not include support for xgetbv and
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// there is no easy way to conditionally compile based on the assembler used.
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int rEAX, rEDX;
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__asm__ __volatile__(".byte 0x0f, 0x01, 0xd0" : "=a"(rEAX), "=d"(rEDX) : "c"(0));
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return (rEAX & 0x60000) == 0x60000;
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#endif // !defined(HOST_IS_WINDOWS)
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}
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#endif // !__arm__
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static const char *lGetSystemISA() {
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#if defined(__arm__) || defined(__aarch64__) || defined(_M_ARM64)
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return "ARM NEON";
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#else
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int info[4];
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__cpuid(info, 1);
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int info2[4];
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// Call cpuid with eax=7, ecx=0
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__cpuidex(info2, 7, 0);
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// clang-format off
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bool sse2 = (info[3] & (1 << 26)) != 0;
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bool sse41 = (info[2] & (1 << 19)) != 0;
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bool sse42 = (info[2] & (1 << 20)) != 0;
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bool avx_f16c = (info[2] & (1 << 29)) != 0;
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bool avx_rdrand = (info[2] & (1 << 30)) != 0;
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bool osxsave = (info[2] & (1 << 27)) != 0;
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bool avx = (info[2] & (1 << 28)) != 0;
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bool avx2 = (info2[1] & (1 << 5)) != 0;
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bool avx512_f = (info2[1] & (1 << 16)) != 0;
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// clang-format on
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if (osxsave && avx2 && avx512_f && __os_has_avx512_support()) {
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// We need to verify that AVX2 is also available,
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// as well as AVX512, because our targets are supposed
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// to use both.
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int info3[4] = {0, 0, 0, 0};
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int max_subleaf = info2[0];
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// Call cpuid with eax=7, ecx=1
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if (max_subleaf >= 1)
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__cpuidex(info3, 7, 1);
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// clang-format off
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bool avx512_dq = (info2[1] & (1 << 17)) != 0;
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bool avx512_pf = (info2[1] & (1 << 26)) != 0;
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bool avx512_er = (info2[1] & (1 << 27)) != 0;
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bool avx512_cd = (info2[1] & (1 << 28)) != 0;
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bool avx512_bw = (info2[1] & (1 << 30)) != 0;
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bool avx512_vl = (info2[1] & (1 << 31)) != 0;
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bool avx512_vbmi2 = (info2[2] & (1 << 6)) != 0;
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bool avx512_gfni = (info2[2] & (1 << 8)) != 0;
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bool avx512_vaes = (info2[2] & (1 << 9)) != 0;
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bool avx512_vpclmulqdq = (info2[2] & (1 << 10)) != 0;
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bool avx512_vnni = (info2[2] & (1 << 11)) != 0;
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bool avx512_bitalg = (info2[2] & (1 << 12)) != 0;
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bool avx512_vpopcntdq = (info2[2] & (1 << 14)) != 0;
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bool avx_vnni = (info3[0] & (1 << 4)) != 0;
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bool avx512_bf16 = (info3[0] & (1 << 5)) != 0;
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bool avx512_vp2intersect = (info2[3] & (1 << 8)) != 0;
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bool avx512_amx_bf16 = (info2[3] & (1 << 22)) != 0;
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bool avx512_amx_tile = (info2[3] & (1 << 24)) != 0;
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bool avx512_amx_int8 = (info2[3] & (1 << 25)) != 0;
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bool avx512_fp16 = (info2[3] & (1 << 23)) != 0;
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// clang-format on
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// Knights Landing: KNL = F + PF + ER + CD
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// Skylake server: SKX = F + DQ + CD + BW + VL
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// Cascade Lake server: CLX = SKX + VNNI
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// Cooper Lake server: CPX = CLX + BF16
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// Ice Lake client & server: ICL = CLX + VBMI2 + GFNI + VAES + VPCLMULQDQ + BITALG + VPOPCNTDQ
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// Tiger Lake: TGL = ICL + VP2INTERSECT
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// Sapphire Rapids: SPR = ICL + BF16 + AMX_BF16 + AMX_TILE + AMX_INT8 + AVX_VNNI + FP16
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bool knl = avx512_pf && avx512_er && avx512_cd;
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bool skx = avx512_dq && avx512_cd && avx512_bw && avx512_vl;
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bool clx = skx && avx512_vnni;
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bool cpx = clx && avx512_bf16;
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bool icl =
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clx && avx512_vbmi2 && avx512_gfni && avx512_vaes && avx512_vpclmulqdq && avx512_bitalg && avx512_vpopcntdq;
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bool tgl = icl && avx512_vp2intersect;
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bool spr =
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icl && avx512_bf16 && avx512_amx_bf16 && avx512_amx_tile && avx512_amx_int8 && avx_vnni && avx512_fp16;
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#pragma unused(cpx, tgl)
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if (spr) {
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if (__os_enabled_amx_support()) {
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return "SPR (AMX on)";
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} else {
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return "SPR (AMX off)";
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}
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} else if (skx) {
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return "SKX";
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} else if (knl) {
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return "KNL";
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}
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// If it's unknown AVX512 target, fall through and use AVX2
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// or whatever is available in the machine.
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}
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if (osxsave && avx && __os_has_avx_support()) {
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// AVX1 for sure....
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// Ivy Bridge?
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if (avx_f16c && avx_rdrand) {
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// So far, so good. AVX2?
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if (avx2) {
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return "AVX2 (codename Haswell)";
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} else {
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// Ivy Bridge specific target was deprecated in ISPC, but
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// no harm detecting it in standalone tool.
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return "AVX1.1 (codename Ivy Bridge)";
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}
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}
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// Regular AVX
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return "AVX (codename Sandy Bridge)";
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} else if (sse42) {
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return "SSE4.2";
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} else if (sse41) {
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return "SSE4.1";
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} else if (sse2) {
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return "SSE2";
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} else {
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return "Error";
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}
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#endif
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}
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int main() {
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const char *isa = lGetSystemISA();
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printf("ISA: %s\n", isa);
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return 0;
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}
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